Semiconductor devices based on vertical IGFET (insulated gate field effect transistor) cells include cell trench structures with buried electrodes and semiconductor mesas between the cell trench structures. Typically a photolithographic mask defines placement and size of the cell trench structures and another photolithographic mask defines placement and size of contact structures providing electric contacts to impurity zones in the semiconductor mesas. Other approaches rely on forming the contact structures self-aligned to the cell trench structures. It is desirable to provide semiconductor devices with narrow semiconductor mesas and small distances between neighboring cell trench structures in a reliable way and at low costs.